PVSim 6.0.2 Beta
PVSim 6.0.2 Beta summary
PVSim 6.0.2 Beta screenshot
PVSim 6.0.2 Beta description
PVSim is designed to offer users an intuitive emulation utility for the Verilog hardware description language.
With its fast simulation runtime and the user-friendly interface, PVSim can open and simulate PSIM files, enabling you to view the results within its main window, together with the simulation parameters and the event log.
What's New in This Release:
· Added ability to open and simulate a given .psim file
· Improved defaults for window and pane sizes, locations
· Added example1.py as default psim file, copied in as needed
· Fixed Command-arrow key combinations to scroll to ends
· Fixed Find scrolling and remembering string, and added wrap
· Fixed scrolling so it stays put after a cut or paste
· Adjusted signal text baseline for Mac
· Added "While locating bit events for bus" hang error checking
· Improved error catching and reporting from backend
· Fixed exit() to return successful 0
· Fixed launching with "python pvsim.py" case
· Added auto version extraction to setup_ext.py
· Fixed pvsimu top-level make
· Fixed PVSim_Dev.app to always use the latest pvsimu extension
· Windows: added winpack.bat to simplify exe creation
· Windows: added Inno installer script
PVSim 6.0.2 Beta keywords
PVSim 6.0.2 Beta for Developers
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